Semiconductor memory devices are typically classified into volatile memory devices and non-volatile memory devices. Volatile memory devices are subdivided into dynamic random access memories (DRAMs) and static random access memories (SAMs). Non-volatile memory types include mask read-only memories (MROMs), programmable read-only memories (PROMs), erasable programmable read-only memories (EPROMs), and electrically erasable programmable read-only memories (EEPROMs). EEPROMs are increasingly used in systems programming that requires continuous update or auxiliary memory devices. Particularly, flash EEPROMs are advantageous as mass storage devices because their integration density is high compared with conventional EEPROMs.
FIG. 1 shows a prior art EEPROM memory cell 100. The memory cell 100 includes an NMOS select transistor 101, an NMOS memory transistor 103, a bit line, terminal 105, an NMOS-NMOS drain junction 107, and a source terminal 109. A contemporary EEPROM uses NMOSfets for both the NMOS select transistor 101 and the NMOS memory transistor 103. Fabrication difficulties currently arise if different device types are employed. However, this same NMOS-NMOS arrangement requires a programming potential as high as 14 volts. Although the tunneling current through a typical 7 nanometer (nm) thick tunnel diode window can be injected with only 10 volts, the higher 14 volt programming potential is required due to a voltage drop across the select transistor 101. This voltage drop will depend on factors such as transistor threshold voltage and body effects, but can be about 3 volts or more. For example, a 14-volt programming pulse on the bit line terminal 105 may produce only 11 volts at the NMOS-NMOS drain junction 107.
Accordingly, what is needed is a way to provide an improved process and structure capable of programming an EEPROM device at about 10 volts, thereby allowing an integration into existing processes without adding additional or complex masks. Such a device would also, for example, allow for EEPROM integration into a 3.3 volt CMOS technology. Such a structure must be economical to manufacture and readily adaptable to contemporary integrated circuit fabrication facilities.